EDN

Recursive clock gating: Performance implications

With so much buzz around low power wearable electronics, designers are looking to save every last nanowatt of power in their design. Clock gating, which arguably is the most efficient and most simple ...
EDN

Pitfalls of state-transition clock gating

Clock gating is the most commonly employed design technique to save dynamic power, and one can find a plethora of technical literature on it and associated techniques. However, many implementations ...
Electronic Design

Reduce Power in Chip Designs with Sequential Clock Gating

Clock gating is one of the most frequently used techniques in RTL to reduce dynamic power consumption without affecting the functionality of the design. One method involves inserting gating conditions ...
Electronic Design

1.5-GHz FPGA Takes Clock Gating To The Max

Flexibility is key to FPGA success, but speed is equally important. Achronix almost triples the throughput of the system by taking clock gating to the extreme. The Achronix Speedster FPGAs use a ...
Embedded

Static timing analysis: bridging the gap between simulation and silicon

Static Timing Analysis (STA) not only acts as a connecting link between backend and frontend design activities, but more importantly helps in bridging the gap between simulation and silicon. STA is ...